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| 01W095A Clock generator for digital still camera BU2382FV Description BU2382FV is a high-performance 2-channel PLL IC. PLL circuit generates necessary clocks by inputting standard clocks of crystal oscillator from outside. Changing a connection of wire can generate any clocks required for any applications of users. Jitter and S/N characteristic has achieved almost the same high-quality sound and vision as oscillating module because of optimization of PLL. Frequency can be changed by the internal dividing control. Dimension (Units : mm) 5.0 0.2 1.15 0.1 6.4 0.3 0.1 4.4 0.2 16 9 1 8 0.15 0.1 0.65 0.1 0.22 0.1 SSOP-B16 Features 1) Generate clocks for CDS, USB with standard clock input 2) No external elements required 3) Standard clocks apply to two kinds of NTSC/PAL 4) Power down control in each 2-channel PLL 5) Single power supply of 3.3V operating 6) SSOP-B16 small package Applications Digital still camera Absolute Maximum Ratings (Ta=25C) Parameter Applied voltage Input voltage Storage temperature range Power dissipation Symbol VDD VIN Tstg PD -0.5 -0.5 -30 Limits Unit V V ~ +7.0 ~ VDD+0.5 ~ +125 450 C mW *IC destruction is not occurred, however, operation can not be guaranteed. *Derating : 4.5mW/C for operation above Ta=25C *This product is not designed for protection against radioactive rays. *Power dissipation is the rate when the IC is mounted on the board. October, 2001 0.3Min. Recommended Operating Conditions (Ta=25C) Parameter Power supply voltage Input H voltage range Input L voltage range Operating temperature Output load Symbol VDD VIH VIL Topr CL Min. 3.0 0.8VDD 0 -5 - Typ. - - - - - Max. 3.6 VDD 0.2VDD 70 15 Unit V V V C pF Electrical Characteristics (Unless otherwise noted; Ta=25C, Vcc=3.3V, Xtal frequency=14.318182MHz) Parameter Output H voltage Output L voltage Input thL *3 Input thH *3 Hysteresis width *3 Operating circuit current Symbol VOH VOL VthL VthH Vhys IDD CLK1_LL CLK1 CLK1_LH CLK1_HL CLK1_HH CLK2_L CLK2_H Duty JsSD JsABS tr tf tlock - Min. 2.4 - 0.2VDD - - - Typ. - - - - 0.4 30 48.626786 70.937900 48.461539 71.877274 47.998742 47.998451 Max. - 0.4 - 0.8VDD - 45 Unit V V V V V mA Conditions IOH=-4.0mA IOL=4.0mA *1 *1 Vhys=VthH-VthL No load XTAL170/31/2 (XTAL=17.734475MHz) XTAL360/45/2 (XTAL=17.734475MHz) XTAL176/26/2 (XTAL=14.318182MHz) XTAL502/50/2 (XTAL=14.318182MHz) XTAL249/46/2 (XTAL=17.734475MHz) XTAL295/44/2 (XTAL=14.38182MHz) - MHz CLK2 Duty Jitter Jitter Min.-Max. Rise time Fall time Output Lock time - 45 - - - - - - 55 - - - - 1 MHz % psec psec nsec nsec msec 50 30 180 2.5 2.5 - 1/2VDD test 1short time jitter Min.-Max. 20% ~ 80% time of VDD 20% ~ 80% time of VDD *2 Output (V) 0.2VDD Vhys 0.8VDD Note) Output frequency is determined by the operation expression (Frequency divide) input to XTAL IN. Output at 27MHz input is shown above. Jitter is value when using Time interval analyzer with 10000 sampling. *| 1*j Low and high limit voltage in the schmitt trigger input Pin having hysteresis features shown in *| 3 diagram. *| 2*j Time that output takes to stabilize in the specific frequency range after the power supply reaches to 3.0V. *| 3*j Make reference to the diagram. Block Diagram VthL 1/2VDD VthH Input(V) 1 2 N T:14.38182MHz PAL:17.734475MHz VDD2 OE_CLK1 16 15 14 13 12 11 10 9 H or L CLK1 output H or L H or L VSS2 REF_CLK CLK1 3 4 5 6 7 8 SEL TEST1 NT_PAL AVDD DVDD AVSS DVSS XTALIN CLK2 CLK2 output H or L XTALOUT BU2382FV OE_CLK2 |
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